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Chapter 3 Interrupts
Control Registers
■ATC 1 Interrupt Control Register (ATC1ICR)
The ATC 1 interrupt control register (ATC1ICR) controls interrupt level of ATC 1 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
Figure 3-2-26 ATC1 Interrupt Control Register (ATC1ICR : x'03FFC', R/W)
ATC1
LV1
Interrupt level flag
ATC1
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
ATC1IE
ATC1IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
ATC1IE
ATC1IR
----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
ATC1
LV0
ATC1
LV1
ATC1ICR