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Chapter 3 Interrupts
Control Registers
■Serial Interface 0 Transmission Interrupt Control Register (SC0TICR)
The serial Interface 0 transmission interrupt control register (SC0TICR) controls interrupt level of serial
Iinterface 0 transmission interrupt, interrupt enable flag and interrupt request. Interrupt control register
should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-19 Serial Interface 0 Transmission Interrupt Control Register
(SC0TICR : x'03FF5', R/W)
SC0T
LV1
Serial interface 0 transmission
interrupt level flag
SC0T
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Serial interface 0 transmission
interrupt request flag
Interrupt request generated
SC0TIE
SC0TIR
0
1
Disable interrupt
Serial interface 0 transmission
interrupt enable flag
Enable interrupt
SC0TIE
SC0TIR
----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
SC0T
LV0
SC0T
LV1
SC0TICR