Filter
Top Products
Chapter 3 Interrupts
III - 24
Control Registers
■Timer 4 Interrupt Control Register (TM4ICR)
The timer 4 interrupt control register (TM4ICR) controls interrupt level of timer 4 interrupt, interrupt
enable flag and interrupt request. Interrupt control register should be operated when the maskable inter-
rupt enable flag (MIE) of PSW is "0".
Figure 3-2-12 Timer 4 Interrupt Control Register (TM4ICR : x'03FED', R/W)
TM4
LV1
Interrupt level flag
TM4
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
TM4IE
TM4IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
TM4IE
TM4IR----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
TM4
LV0
TM4
LV1
TM4ICR