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Chapter 15 A/D Converter
Operation
XV - 8
15-3 Operation
Here is a description of A/D converter circuit setup procedure.
(1) Set the analog pins.
Set the analog input pin, set in (2), to "special function pin" by the port A input mode register
(PAIMD).
* Setup for the port A input mode register should be done before analog voltage is put to pins.
(2) Select the analog input pin.
Select the analog input pin from AN6 to AN0 (PA6 to PA0) by the ANCHS2 to ANCHS0 flag of
the A/D converter control register 1 (ANCTR1).
(3) Select the A/D converter clock.
Select the A/D converter clock by the ANCK1, ANCK0 flag of the A/D converter control
register 0 (ANCTR0).
Setup should be such a way that converter clock (TAD) does not drop under 800 ns with any
oscillator.
(4) Set the sample hold time.
Set the sample hold time by the ANSH1, ANSH0 flag of the A/D converter control register 0
(ANCTR0). The sample hold time should be based on analog input impedance.
(5) Set the A/D ladder resistance.
Set the ANLADE flag of the A/D converter control register 0 (ANCTR0) to "1", and a current
flow through the ladder resistance and A/D converter goes into the waiting.
* (2) to (5) are not in order. (3), (4) and (5) can be operated simultaneously.
(6) Select the A/D converter activation factor, then start A/D conversion.
Set the ANST flag of the A/D converter control register 2 (ANCTR2) to "1" to start A/D
converter, or set the ANSTSEL flag of the A/D converter control register 2 (ANCTR2) to "1" to
start A/D conversion by the external interrupt IRQ3.
* Specify the valid edge by the EDGSEL3 flag of the both edges interrupt control register
(EDGDT) and the REDG3 flag of the external interrupt 3 control register (IRQ3ICR).
(7) A/D conversion
Each bit of the A/D buffer 0,1 is generated after sampling with the sample and hold time set in
(3). Each bit is generated in sequence from MSB to LSB.
(8) Complete the A/D conversion.
When A/D conversion is finished, the ANST flag is cleared to "0", and the result of the
conversion is stored to the A/D buffer (ANBUF0, 1). At the same time, the A/D complete
interrupt request (ADIRQ) is generated.