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Chapter 4 I/O Ports
IV - 22
Port 5
4-5-2 Registers
Figure 4-5-1 Port 5 Registers
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P5OUT
P5OUT4 P5OUT3 P5OUT2 P5OUT1 P5OUT0
0
1
Low (VSS level)
Output data
High (V
DD level)
P5OUT
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P5IN
P5IN4 P5IN3 P5IN2 P5IN1 P5IN0
0
1
Pin is Low (VSS level).
Input data
Pin is High (V
DD level).
P5IN
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P5DIR
P5DIR4 P5DIR3 P5DIR2 P5DIR1 P5DIR0
0
1
Input mode
I/O mode selection
Output mode
P5DIR
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P5PLU
P5PLU4 P5PLU3 P5PLU2 P5PLU1 P5PLU0
0
1
No pull-up resistor
Pull-up resistor selection
Pull-up resistor
P5PLU
Port 5 output register (P5OUT : x'03F15', R/W)
Port 5 input register (P5IN : x'03F25', R)
Port 5 direction control register (P5DIR : x'03F35', R/W)
Port 5 pull-up resistor control register (P5PLU : x'03F45', R/W)
( At reset : - - - 0 0 0 0 0 )
( At reset : - - - 0 0 0 0 0 )
( At reset : - - - X X X X X )
( At reset : - - - 0 0 0 0 0 )