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Chapter 3 Interrupts
III - 30
Control Registers
■Serial Interface 0 Reception Interrupt Control Register (SC0RICR)
The serial Interface 0 reception interrupt control register (SC0RICR) controls interrupt level of serial
Interface 0 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register
should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-18 Serial Interface 0 Reception Interrupt Control register
(SC0RICR:x'03FF4', R/W)
SC0R
LV1
Serial interface 0 reception
interrupt level flag
SC0R
LV0
01245673
(at reset : 0 0 - - - - 0 0 )
0
1
No interrupt request flag
Serial interface 0 reception
interrupt request flag
Interrupt request generated
SC0RIE
SC0RIR
0
1
Disable interrupt
Serial interface 0 reception
interrupt enable flag
Enable interrupt
SC0RIE
SC0RIR
----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
SC0R
LV0
SC0R
LV1
SC0RICR