Filter
Top Products
III - 21
Chapter 3 Interrupts
Control Registers
■External Interrupt 4 Control Register (IRQ4ICR)
The external interrupt 4 control register (IRQ4ICR) controls interrupt level of external interrupt 4, active
edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the
maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-6 External Interrupt 4 Control Register (IRQ4ICR : x'03FE6', R/W)
IRQ4
LV1
Interrupt level flag for external interrupt
IRQ4
LV0
01245673
(At reset : 0 0 0 - - - 0 0)
IRQ4ICR
0
1
No interrupt request
External interrupt request flag
Interrupt request generated
IRQ4IE
IRQ4IR
0
1
Disable interrupt
External interrupt enable flag
Enable interrupt
IRQ4IE
0
1 Rising edge
External interrupt active edge flag
Falling edge
The CPU has interrupt levels from 0 to 3. These
flags set the interrupt level for interrupt requests.
REDG4
IRQ4IR
IRQ4
---
LV1
IRQ4
LV0
REDG4