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Chapter 3 Interrupts
Control Registers
■Timer 7 Compare Register 2-match Interrupt Control Register (TOC2ICR)
The timer 7 compare register 2-match interrupt control register (TOC2ICR) controls interrupt level of
timer 7 compare register 2-match interrupt , interrupt enable flag and interrupt request. Interrupt control
register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Figure 3-2-17 Timer 7 Compare Register 2-match Interrupt Control Register
(TMOC2ICR : x'03FF2', R/W)
T7OC2
LV1
Interrupt level flag
T7OC2
LV0
01245673
(At reset : 0 0 - - - - 0 0)
0
1
No interrupt request
Interrupt request flag
Interrupt request generated
T7OC2
IE
T7OC2IR
0
1
Disable interrupt
Interrupt enable flag
Enable interrupt
T7OC2IE
T7OC2
IR
----
The CPU has interrupt levels from 0 to 3.
These flags set the interrupt level for
interrupt requests.
T7OC2
LV0
T7OC2
LV1
T7OC2ICR